I/o and Computation Overlap on Simd Systolic Arrays Dominique Lavenier, Frédéric Raimbault, Patrice Frison

I/O and computation overlap on SIMD systolic arrays

A mechanism for overlapped I/O management operations and computation on a simd linear systolic array is presented. This mechanism is based on two synchronized controllers allowing a speedup factor of 2 over simd machines without overlapped facility. Code generation is achieved using the C-stolic language, specifically designed for the architectural features of overlapped simd systolic arrays. R...

ReLaCS for Systolic Programming

The ReLaCS language is a systolic programming language, which simpliies the programmer's task by making explicit the data-ow of systolic algorithms, and by exposing the data delivery mechanism. The underlying architecture model is diierent from other SIMD architectures in that it physically separates computation and data management. We introduce the ReLaCS language as a syntaxic and a semantic ...

From Equations to Hardware: Towards Systematic Mapping of Algorithms onto Parallel Architectures

726 Relacs for Systolic Programming

The ReLaCS language is a systolic programming language, which simpliies the programmer's task by making explicit the data-ow of systolic algorithms, and by exposing the data delivery mechanism. The underlying architecture model is diierent from other SIMD architectures in that it physically separates computation and data management. We introduce the ReLaCS language as a syntaxic and a semantic ...

Fine grain parallelism on a MIMD machine using FPGAs

Current MIMD machines are used for coarse grain-parallelism and also ooer messsage passing mechanisms to deal with inter-processor communications. But these mechanisms lack eeciency in ne-grain parallel applications such as systolic computation. This article presents the use of an FPGA chip to set up a fast systolic communication agent on a linear asynchronous network of Transputer processors; ...